The present invention relates generally to semiconductor integrated circuits (IC) and, more particularly, to a delay locked loop (DLL) circuit included in a semiconductor IC and a method of controlling the same.
A conventional semiconductor IC, such as, synchronous dynamic random access memory (SDRAM), uses a clock signal to increase an operational speed. For this, a typical semiconductor IC includes a clock buffer that buffers an externally input clock signal. In some cases, a semiconductor IC includes a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate an internal clock signal in which a phase difference between the internal clock signal and the external clock signal has been corrected. With respect to the internal clock signal used in a semiconductor IC, a ratio between a high level interval and a low level interval, i.e., a duty ratio, is preferably maintained at a predetermined ratio of 50:50. However, since the typical semiconductor IC includes numerous delay elements, the duty ratio of the internal clock signal may easily vary.
Due to the high-speed operations of semiconductor ICs, utilization of a clock signal has increased, thus, a clock signal having a stable duty ratio is required. Accordingly, the DLL circuit of each semiconductor IC has a configuration for performing a duty cycle correcting function and an importance of a duty cycle correcting technology using the configuration has increased in order to utilize a stable clock signal in a high-speed operation.
The DLL circuit that performs the duty cycle correcting operation is implemented as a dual loop type. One of two feedback loops performs a delay lock operation and the other performs the duty cycle correcting operation. That is, the first feedback loop includes a replica delayer and a phase detector and controls a phase of an output clock signal by adjusting a delay value of a first delay line, while the second feedback loop controls a duty cycle of the output clock signal by detecting the duty cycle of the output clock signal and adjusting a delay value of a second delay line.
However, the dual loop type DLL circuit includes two delay lines, such that the area occupied thereof increases. Actually, the second delay line that performs the duty cycle correcting operation has a variation of the delay value smaller than the first delay line that performs the delay lock operation. However, it is not easy that the first delay line and the second delay line are configured to have different total delay values from each other in the above-mentioned structure. As the semiconductor IC is implemented with high integration, the area occupied by the DLL circuit being large as described above is recognized as a concern to be addressed.